Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability

High-density and high-performance single-port and dual-port SRAM increasingly occupy a majority of the chip area in System-on-Chip product designs. Therefore, good yieldability and manufacturability of the SRAM are essential. At the same time there is tremendous competitive pressure to get the best SRAM density and performance. We have previously published and presented the industry’s smallest and fastest embedded 6T SRAM bitcells in 0.18um and 130nm generation standard CMOS process [1]. We have described how these SRAM bitcells are robust by design even while aggressively driving density and performance. In this paper we discuss the design and use of SRAM-specific test structures that have enabled us to quickly evaluate process-design interactions [2] and to fine-tune process and/or design for improving yields and manufacturability. We have designed test structures using our aggressive production bitcell as basis to probe for any possible weaknesses of the process or design in SRAM. Results from these SRAM-specific test structures show good correlation to yield results and in-line SEM observations, and enable us to improve SRAM yields quickly. We have also designed SRAM-transistor test structures to characterize the SRAM cell devices in their real working environment. Results help to evaluate the circuit performance and provide us with guidelines for further design improvements. These data when used in the early stage of the development cycle are also useful for model validation.